It is often desirable to improve the efficiency and comprehensiveness of manufacturing testing of computer components. To ensure fast and reliable operation of a computer, manufacturing testing of each part must include some form of speed testing to show that the component is operating within the specified timing parameters. In general, such functional testing includes a tester that provides inputs to the chip and receives an output pattern from the chip. The tester compares the output to an expected value to determine if the chip is operating properly. In addition, the functional testing is typically cycle deterministic in that the tester receives the output from the chip synchronously with the tester clock. The cycle deterministic functional testing of the chip provides the tester with verification of the chips operability.
However, providing cycle deterministic outputs to the tester during the functional testing may be problematic as more and more chips incorporate asynchronous clock domains within the chip design. As a result, the output of the chips to the tester may arrive at either before or after the expected arrival time of the output. Previously, testers have addressed this by conducting the test at a low frequency so that the output to the tester is cycle deterministic. However, such low frequency tests are not at-speed such that an accurate testing of the chip does not occur. Other chip manufacturers provide a synchronous mode design within the chip that allows for cycle deterministic testing. However, such synchronous mode designs consume valuable hardware area and power that cause the chip to operate less efficiently.
It is with these and other issues in mind that various aspects of the present disclosure were developed.